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  • br Bipartite graph br Algorithm for

    2021-04-13


    Bipartite graph
    Algorithm for CFC
    Error detection rate and overhead evaluation
    Test results and discussion For verifying the proof in Fmoc-Gly-OPfp from the perspective of practice, this section brings tests and analysis based on the onboard computer (OBC) of the in-service ZDPS-1A pico-satellite, which are researched and developed by our institute. The OBC utilizes an 8-bit 8052-compatible Harvard architecture COTS processor ADuC841 from Analog Devices, which contains a 2KB random access memory (RAM) for data storage and a 64KB read only memory (ROM) for code storage. The program code is executed in the ROM directly. ADuC841 is a simple controller and lacks the specific hardware for calculation, such as multipliers. One of the successive products of ZPDS-1A utilizes a more powerful 32-bit COTS digital signal processor (DSP) TMS320C6747 from Texas Instruments, which features the Harvard architecture too. TMS320C6747 equips various controllers, multipliers and signal processing units; it is much more powerful than ADuC841. However, we still choose the ADuC841 instead of TMS320C6747 as the test bench based on the following reasons. Firstly, the main purpose of this paper is to supply a generic high-performance and low-overhead SCFC techniques for COTS-based small satellites, not just limited to our own products. However, TMS320C6747 is powerful and may hide the shortages of the propose method, because not all processors in small satellites are as powerful as TMS320C6747. Secondly, according to the survey,1, 23 mainstream small satellites adopted Harvard architecture processors, such as ARM, PIC controller, DSP etc. ADuC841 is generally less powerful than them, so if BGCFC is verified to be applicable for ADuC841, then we believe it will be generally adequate for most processors of mainstream small satellites. Thirdly, ZDPS-1A has successfully fulfilled all the missions and been functionally well in aerospace for more than three years, so we believe the OBC of ZDPS-1A is reliable and Phase variation will not introduce extra unsafe factors to affect the accuracy of test results. Finally yet importantly, the goal of BGCFC is to extend the lifecycle of the small satellites in real projects, not only limited to the academic research. We generate six versions for each benchmark, which are: Table 1 shows the comparison results of the time and memory overhead for each version of benchmark. Note that the results of MM and FFT hardened by CFCSS are much lower than the results in the original paper because the ADuC841 lacks the multiplier while MM and FFT employ heavy multiplications, both the execution time and memory size increase, but the MIPS processor adopted by the original paper contains a multiplier. Checking instructions inserted by CFCSS contain only simple XOR and AND operations which does not increase the execution time and memory size. Therefore, the increasing ratio of execution time and memory size decreases accordingly, resulting in that CFCSS has both low time and memory overhead. SCFC gets large time and memory overhead because the number of basic blocks N is larger than 8 (word length of ADuC841), a single operation of the bitmap needs to be divided into multiple operations, which increases the time and memory overhead. ECCA leads to large performance decay due to the numerous multiplications in the checking instructions, which shows obviously in IS and QS because these two benchmarks contain no multiplication. The results of MM and FFT seem better because both benchmarks and checking instructions contain numerous multiplications so that the ratios are pulled down. The time overhead of GTCFC is a little bit larger than CFCSS due to the slow indirect addressing and the extra overhead of virtual basic blocks, but the memory overhead is significantly large due to the linear memory space complexity. BGCFC is the only one that is comparable with CFCSS in both time and memory overhead.